SOC Timing/Methodology Intern

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies – from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx’s core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore’s Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

This Intern/Co-op position may involve one or more of SOC Design/ Analysis activities such as:
– Circuit simulation and optimization
– Digital design using Verilog
– Synthesis, Place and Route
– Static Timing Analysis, Spice simulations
– Electrical EMIR/ Power analysis
– Scripting using TCL, PERL, Python
– CAD flow development
– Data analysis and processing

– MSEE or PhD student in EE or CS
– Complete knowledge of basic digital circuit design principles
– Knowledge of static timing analysis, power optimization, low power design concepts
– Knowledge of ASIC or FPGA design flows
– Knowledge of RTL design in Verilog/SystemVerilog
– Knowledge of Algorithm designs and programming/ scripting languages

Experience in following is desired:
– Verilog HDL, System Verilog
– TCL, Perl, Python scripting
– Synopsys Design Compiler, PrimeTime, HSpice, Redhawk
– Simulation environment such as VCS, Questa
– Version control systems such as Perforce, ICManage
– Good communication (verbal and written) and presentation skills
– Good organization and self-starter

To apply, please contact Alvin Ching at