Challenges Trends For 28 Nm And Below In Soc Analog Mixed Signal Design

In this presentation we review current and future trends and challenges for system on chip analog/mixed signal design for CMOS nodes in 28 nm and below. We review our recent developments in clocking, phased locked loop, higher performance I/O and SerDes designs. In addition we will give real world examples of Analog Bit solutions, which have shipped in billions of units in a variety of today’s highest performance consumer platforms.
Specifically we discuss development of industry leading and industry firsts including: (1) development of a CMOS 20nm mixed signal design kit, (2) successful design of high‐performance PLL at very low dissipated power levels for 100GB applications including implementation of a 14GHz SerDes PLL in TSMC 28nm technology which produces quadrature outputs and a measured output clock jitter < 0.3ps rms in under 12mW of power and (3) development of a PLL used in 100GBASE-LR4 and Optical Transport Lane 4.4 SerDes applications incorporating an LC-VCO running at 12.5-14.5GHz and generates quadrature outputs at 6.25-7.25 GHz. Fabricated in 40nm GP CMOS technology, the PLL operates on two supplies: 1.25V for the VCO and 1V for the rest of the circuitry with a measured output clock jitter at the transmitter output at 7 GHz output frequency of 174fsrms while consuming 12mW.